Analytic modeling

The Execution-Cache-Memory (ECM) performance model

The ECM model was created in 2009 as part of an effort to better understand the performance behavior of multi-core processors with complex cache/memory hierarchies. Although the well-tried Roofline model delivers correct full-chip performance estimates for such processors, it turns out the model’s premise of performance being constrained either by sustained main memory bandwidth or peak floating-point performance proves too optimistic for most real hardware. The ECM model solves this problem by modeling instruction-execution and data-movement times separately. By combining these contributions according to a processors capability to overlap the contributions, the model enables high-accuracy performance estimates for data sets in all levels of the memory hierarchy. Moreover, the model’s multi-core estimates can accurately predict performance for arbitrary numbers of active cores, instead of just full-chip estimates as is the case for the Roofline model.

Publications

    • Johannes Hofmann, Christie Lous Alappat, Georg Hager, Dietmar Fey, Gerhard Wellein. (2020). Bridging the architecture gap: Abstracting performance-relevant properties of modern server processors. Supercomputing Frontiers and Innovations, 7(2), 54-78. https://dx.doi.org/10.14529/jsfi200204
    • Johannes Hofmann. A First-Principles Approach to Performance, Power, and Energy Models for Contemporary Multi- and Many-Core Processors. PhD thesis, Friedrich- Alexander-University Erlangen-Nuremberg, Munich, Germany, October 2019
    • Johannes Hofmann, Georg Hager, and Dietmar Fey. On the Accuracy and Usefulness of Analytic Energy Models for Contemporary Multicore Processors. In Rio Yokota, Michèle Weiland, David Keyes, and Carsten Trinitis, editors, High Performance Computing: 33rd International Conference, ISC High Performance 2018, Frankfurt, Germany, June 24–28, 2018, Proceedings, pages 22–43, Cham, 2018. Springer International Pub- lishing. ISBN 978-3-319-92040-5. URL http://doi.org/10.1007/978-3-319-92040-5_2
    • Jan Laukemann, Julian Hammer, Johannes Hofmann, Georg Hager, and Gerhard Wellein. Automated Instruction Stream Throughput Prediction for Intel and AMD Microarchitectures. In Proceedings of PMBS 2018: Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems, held as part of ACM/IEEE Supercomputing 2018 (SC18), Dallas, TX, November 12, 2018, pages 121–131, Washington, DC, USA, 2018. IEEE Computer Society. ISBN 978-1-7281-0182-8. URL http: //doi.org/10.1109/PMBS.2018.8641578
    • Johannes Hofmann, Georg Hager, Gerhard Wellein, and Dietmar Fey. An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors. In Julian M. Kunkel, Rio Yokota, Pavan Balaji, and David Keyes, editors, High Performance Computing: 32nd International Conference, ISC High Performance 2017, Frankfurt, Germany, June 18–22, 2017, Proceedings, pages 294–314, Cham, 2017. Springer International Publishing. ISBN 978-3-319-58667-0. URL http://doi.org/ 10.1007/978-3-319-58667-0_16
    • Johannes Hofmann, Dietmar Fey, Michael Riedmann, Jan Eitzinger, Georg Hager, and Gerhard Wellein. Performance analysis of the Kahan-enhanced scalar product on cur- rent multi-core and many-core processors. Concurrency and Computation: Practice and Experience, 29(9), 2017. ISSN 1532-0634. URL http://doi.org/10.1002/cpe.3921
    • Johannes Hofmann and Dietmar Fey. An ECM-based Energy-efficiency Optimization Approach for Bandwidth-limited Streaming Kernels on Recent Intel Xeon Processors. In Proceedings of the 4th International Workshop on Energy Efficient Supercomputing, E2SC ’16, pages 31–38, Piscataway, NJ, USA, 2016. IEEE Press. ISBN 978-1-5090-3856-5. URL http://doi.org/10.1109/E2SC.2016.16
    • Johannes Hofmann, Dietmar Fey, Jan Eitzinger, Georg Hager, and Gerhard Wellein. Analysis of Intel’s Haswell Microarchitecture Using the ECM Model and Microbenchmarks. In Frank Hannig, João M. P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, and Jürgen Teich, editors, Architecture of Computing Systems – ARCS 2016: 29th International Conference, Nuremberg, Germany, April 4–7, 2016, Pro- ceedings, pages 210–222, Cham, 2016. Springer International Publishing. ISBN 978-3- 319-30695-7. URL http://doi.org/10.1007/978-3-319-30695-7_16
    • Johannes Hofmann, Jan Treibig, and Dietmar Fey. Technical Report: Execution-Cache-Memory Performance Model: Introduction and Validation. ArXiv e-prints, 2015. URL http://arxiv.org/abs/1509.03118