Mehrdad Biglari

Mehrdad Biglari, M. Sc.

Department Informatik (INF)
Lehrstuhl für Informatik 3 (Rechnerarchitektur)

E-Mail: mehrdad.biglari@fau.de
Webseite: https://www3.cs.fau.de/blog/person/mehrdad-biglari/

Information

Mehrdad? Biglari is a Ph.D candidate in the department of Computer Science at FAU Erlangen-Nürnberg. He is a member of the research staff at the Chair of Computer Architecture supervised by Prof. Dr.-Ing. Dietmar Fey.
Before joining FAU, he received his B.Sc. in Computer Engineering from University of Tehran and his M.Sc. in Computer Engineering from Sharif University of Technology.

Research Interests

Emerging Memory Technologies
Transient Computing
Embedded Systems

Publications

2018

Biglari M., Lieske T., Fey D.:
High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States
14th IEEE/ACM International Symposium on Nanoscale Architectures (Athens, Greece)
In: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, New York, NY, USA: 2018
DOI: 10.1145/3232195.3232217
URL: http://doi.acm.org/10.1145/3232195.3232217
Lieske T., Biglari M., Fey D.:
Multi-Level Memristive Voltage Divider: Programming Scheme Trade-offs
International Symposium on Memory Systems (MEMSYS) (Alexandria, Virginia, 1. Oktober 2018 - 4. Oktober 2018)
In: Proceedings of the International Symposium on Memory Systems, New York, NY, USA: 2018
DOI: 10.1145/3240302.3240430
URL: http://doi.acm.org/10.1145/3240302.3240430

2017

Biglari M., Fey D.:
A Non-Volatile Flip-Flop Using Memristive Voltage Divider
IEEE/ACM Design Automation and Test in Europe (DATE), Workshop on Emerging Memory Solutions - Technology, Manufacturing, Architectures, Design and Test (Lausanne, 31. März 2017 - 31. März 2017)
Biglari M., Fey D.:
Memristive Voltage Divider: A Bipolar ReRAM-based Unit for Non-Volatile Flip-Flops
The International Symposium on Memory Systems (MEMSYS) (Alexandria, VA, 2. Oktober 2017 - 5. Oktober 2017)
In: MEMSYS'17 Proceedings of the International Symposium on Memory Systems 2017
DOI: 10.1145/3132402.3132432
URL: https://dl.acm.org/citation.cfm?id=3132432
Wust D., Biglari M., Knödtel J., Reichenbach M., Söll C., Fey D.:
Prototyping Memristors in Digital Systems with an FPGA-Based Testing Environment
International Symposium on Power and Timing Modeling, Optimization and Simulation (Thessaloniki, 25. September 2017 - 27. September 2017)
In: Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017 27th International Symposium on 2017
DOI: 10.1109/PATMOS.2017.8106978
URL: http://ieeexplore.ieee.org/document/8106978/

2016

Fey D., Reichenbach M., Söll C., Biglari M., Röber J., Weigel R.:
Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits
The International Symposium on Memory Systems (MEMSYS) (Alexandria, VA, 3. Oktober 2016 - 6. Oktober 2016)
In: Proceedings of the Second International Symposium on Memory Systems 2016
DOI: 10.1145/2989081.2989124
URL: https://dl.acm.org/citation.cfm?id=2989124

2015

Biglari M., Barijough KM., Goudarzi M., Pourmohseni B.:
A Fine-Grained Configurable Cache Architecture for Soft Processors
International Symposium on Computer Architecture and Digital Systems (CADS) (Tehran, 7. Oktober 2015 - 8. Oktober 2015)
In: Proceedings of the 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS) 2015
DOI: 10.1109/CADS.2015.7377783
URL: https://ieeexplore.ieee.org/document/7377783/

2013

Biglari M., Qasemi E., Pourmohseni B.:
Maestro: A High Performance AES Encryption/Decryption System
International Symposium on Computer Architecture and Digital Systems (CADS) (Tehran, 30. Oktober 2013 - 31. Oktober 2013)
In: Proceedings of the 17th CSI International Symposium on Computer Architecture and Digital Systems (CADS) 2013
DOI: 10.1109/CADS.2013.6714255
URL: https://ieeexplore.ieee.org/document/6714255/