Johannes Knödtel
Johannes Knödtel, M. Sc.
2022
Interfacing real-time and offline power system simulation tools using UDP or FPGA systems
In: Electric Power Systems Research 212 (2022)
ISSN: 0378-7796
DOI: 10.1016/j.epsr.2022.108490 , , , , , , , , , , :
2021
Mitigating the Effects of RRAM Process Variation on the Accuracy of Artifical Neural Networks
21th International Conference, SAMOS 2021
DOI: 10.1007/978-3-031-04580-6_27 , , , , , , , :
Simulating large neural networks embedding MLC RRAM as weight storage considering device variations
In: Proc. of 12th IEEE Latin America Symposium on Circuits and System 2021
DOI: 10.1109/lascas51355.2021.9459159 , , , , , , :
RISC-V3: A RISC-V Compatible CPU with a Data Path Based on Redundant Number Systems
In: IEEE Access (2021), S. 1-1
ISSN: 2169-3536
DOI: 10.1109/ACCESS.2021.3063238 , , , :
2020
A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories
9th International Conference on Modern Circuits and Systems Technologies, MOCAST 2020 (Bremen, 7. September 2020 - 9. September 2020)
In: 9th International Conference on Modern Circuits and Systems Technologies, {MOCAST} 2020, Bremen, Germany, September 7-9, 2020 2020
DOI: 10.1109/MOCAST49295.2020.9200241 , , , , , :
2019
Simulating memristive systems in mixed-signal mode using commercial design tools
26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 (Genoa, 27. November 2019 - 29. November 2019)
In: 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 2019
DOI: 10.1109/ICECS46596.2019.8964856 , , , :
Optimizing Multi-State Reliability in ReRAM Arrays using an Automated Device Selection Method
MEMRISYS 2019 International Conference on Memristive Materials, Devices & Systems (International Congress Center Dresden, 8. Juli 2019 - 11. Juli 2019) , , , , , :
2018
A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs
28th International Symposium on Power and Timing Modeling, Optimization and Simulation (Platja D’Aro, 2. Juli 2018 - 4. Juli 2018)
In: 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2018
DOI: 10.1109/PATMOS.2018.8464149 , , , , :
A programmable ternary CPU using hybrid CMOS/memristor circuits
In: International Journal of Parallel, Emergent and Distributed Systems (2018), S. 1--21
ISSN: 1744-5760
DOI: 10.1080/17445760.2017.1422251 , , :
2017
Prototyping Memristors in Digital Systems with an FPGA-Based Testing Environment
International Symposium on Power and Timing Modeling, Optimization and Simulation (Thessaloniki, 25. September 2017 - 27. September 2017)
In: Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017 27th International Symposium on 2017
DOI: 10.1109/PATMOS.2017.8106978
URL: http://ieeexplore.ieee.org/document/8106978/ , , , , , :