Farhad EbrahimiAzandaryani
Farhad Ebrahimi Azandaryani, M. Sc.
Profile Info
I am a Hardware and Digital Design Engineer with over four years of experience in designing custom RISC-V CPUs, SoCs, and hardware accelerators. I currently work as a Lecturer and Research Assistant at FAU Erlangen-Nürnberg, focusing on FPGA- and ASIC-based hardware development.
For more details, please refer to my Resume , which is available below.
Projects and Research Interests
- NOVACore Demo:(Github)
- RISC-V | Hardware accelerators
- Hardware development with FPGAs
- Low Power and Reconfigurable Computing
Teaching
- Architecture of Supercomputers (ArchSup) Winter 2022/23 – ongoing
- Computer Architecture for Medical Applications (CAMA) Summer 2023 – ongoing
Supervised M.Sc. | B.Sc. Thesis
If you’re a bachelor’s or master’s student looking for a thesis topic and your research background aligns with mine, feel free to reach out—I’d be happy to discuss potential opportunities with you!
Publications
- A. Abdelhafez, F. EbrahimiAzandaryani , M. Bianconi and D. Fey, “ FPGA Implementation of a Real-Time Application Based on RISC-V Cores ” 2025 IEEE 22nd International Multi-Conference on Systems, Signals & Devices (SSD), Monastir, Tunisia, 2025, pp. 1174-1179.
- F. EbrahimiAzandaryani and D. Fey, “ CSD-Driven Speedup in RISC-V Processor ” In: Lorandel, J., Kamaleldin, A. (eds) Design and Architecture for Signal and Image Processing. DASIP 2025. Lecture Notes in Computer Science, vol 15569. Springer, Cham.
- F. EbrahimiAzandaryani and D. Fey, “ ExTern: Boosting RISC-V core performance using ternary encoding ” Microprocessors and Microsystems , volume 107(2024), https://doi.org/10.1016/j.micpro.2024.105058.
- F. Ebrahimi-Azandaryani , O. Akbari, M. Kamal, A. Afzali-Kusha, and M. Pedram, “ Accuracy configurable adders with negligible delay overhead in exact operating mode ” ACM Trans. Des. Autom. Electron. Syst ., vol. 28, no. 1, pp. 1–14, Jan. 2023.
- F. Ebrahimi-Azandaryani , O. Akbari, M. Kamal, A. Afzali-Kusha, and M. Pedram, “ Block-based carry speculative approximate adder for energy-efficient applications, ”IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 67, no. 1, pp. 137–141, Jan. 2019.
