CHROME: Computing witH Resistive-switching memories to Overcome MEmory wall

Dr. John Reuben

The movement of data between processing and memory units in present day computing systems is their main performance and energy-efficiency bottleneck, often referred to as the ‘von Neumann bottleneck’ or ‘memory wall’. As technology scales down, it is evident that ‘data movement energy’ dominates the ‘computation energy’ i.e the computation in itself consumes only a small fraction of the energy. There has been an ongoing effort to combat the memory wall by bringing the processor and memory unit closer to each other. The emergence of Non-Volatile Memory (NVM) technologies like Resistive RAM (RRAM), Phase Change Memory (PCM) and Spin Transfer Torque-Magnetic RAM (STT-MRAM) has created opportunities to overcome the memory wall by enabling one to compute not just near data, but at the residence of data. The focus of this project is to investigate ways to implement arithmetic operations (e.g adders) in memory arrays so that the memory wall can be overcome. Majority logic is a logic primitive with expressive power i.e. arithmetic operations can be expressed with less gates in majority logic, when compared to Boolean NAND/NOR. Recently, a in-memory majority gate is proposed in [1,2]. By activating three rows of the array simultaneously, the resistance of the RRAM cells in a column are in parallel during the READ operation. Consequently, there is a difference in the magnitude of the effective resistance depending on how many of the three resistances are in LRS (Low Resistance State) or HRS (High Resistance State). A Sense Amplifier (SA) which can accurately sense the effective resistance implements a ‘in-memory’ majority gate. Using this majority gate, arithmetic circuits can be designed in-memory (see [2]). The project explores implementing in-memory adders (32-bit) and other circuits in memory to overcome the ‘memory wall’.

[1] John Reuben, “Binary addition in resistance switching memory array by sensing majority,”in Micromachines , vol. 11, No. 5, 2020. doi: 10.3390 / mi11050496

[2] John Reuben, S. Pechmann, “A Parallel-friendly Majority Gate to Accelerate In-memory Computation”, in IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Manchester, UK, 2020, pp. 1-8. doi: 10.1109 / ASAP49362.2020.00025